Integrated circuit memory devices have been developed which store data for indefinite periods of time and which also have the capability of selectively changing the data stored. Of particular interest here is a nonvolatile memory device which utilizes a memory cell which is completely surrounded by a relatively thick insulating material or dielectric and is thus termed a "floating gate". Nonvolatile memory cells may be arranged, as is known in the art, to construct nonvolatile random access memories (NOVRAMs) and electrically erasable programmable read-only memories (EEPROMs). U.S. Pat. No 4,300,212 and U.S. Pat. No. 4,486,769, for example, disclose a NOVRAM and an EEPROM, respectively.
Some EEPROMs made with the so called "thin oxide" technology utilize relatively thin layers of insulating silicon dioxide with two different thicknesses. However, EEPROMs made with this technology have a region of ultra thin (80 to 150 Angstroms) dielectric through which bi-directional tunneling occurs between a smooth single crystal surface and a polysilicon layer.
The fabrication of a memory cell typically consists of depositing and patterning layers of polysilicon with layers of insulating oxide in between. Patterning may be done using conventional photolithographic techniques well known in the industry. More specifically, first polysilicon layer is formed and patterned on a first dielectric layer formed on silicon substrate. A second dielectric layer is then formed to completely surround the first polysilicon layer and to form a tunneling oxide on the surface of the first polysilicon layer. A second polysilicon layer is formed and patterned on top of the second dielectric layer. A third dielectric layer is formed on the second polysilicon layer such that the second polysilicon layer is completely surrounded by dielectric. A third polysilicon layer is then formed and patterned on top of the third dielectric layer. Finally, a fourth dielectric layer is deposited over the entire memory cell.
Typically, the first polysilicon layer is a programming electrode, the second polysilicon layer is the floating gate, and the third polysilicon layer is an erase electrode. The floating gate generally lies between the programming electrode and the erase electrode and partially overlies the former and is itself partially overlain by the latter. Beneath and insulated from the floating gate is the substrate. In one configuration, there is an electrically isolated bias electrode disposed in the substrate of opposite conductivity to the substrate. This bias electrode forms one plate of a coupling capacitor to the floating gate and is also referred to as a metallurgical "paddle". In another configuration there is no metallurgical paddle disposed in the substrate.
Programming, erasing, and retaining information on the floating gate is achieved by controlling the flow of electrons to and from the floating gate. Since the polysilicon layers are insulated from each other by the layers of oxide, the electrons must "tunnel" either from the programming electrode to the floating gate or from the floating gate to the erase electrode. The electron tunneling is controlled by the relative potentials between the electrodes and the floating gate.
The floating gate voltage operating window is defined to be the difference between the positive potential on the floating gate when the floating gate has been erased and the level of negative potential on the floating gate when the floating gate has been programmed. Favorable operating conditions are obtained when this operating window is large and remains large. As the device is alternately programmed and erased, the size of the operating window decreases, thereby shortening the remaining usable lifetime of the device. Thus, a continuing objective of floating gate devices is to increase the operating window size and to maintain that increased window size for a greater number of program and erase cycles, thereby increasing the useful lifetime of the device.
A generally desirable objective of most semiconductor devices is miniaturization. As devices become smaller, however, any misalignment of the polysilicon layers will produce changes in the capacitance between the layers which adversely affects the operation of the device.
Accordingly, it is an object of the present invention to provide a memory cell which reduces alignment sensitivity between polysilicon layers by forming a second thicker dielectric layer between the polysilicon layers in all areas except for those regions where tunneling is to occur.
It is a further object of the present invention to provide a memory cell having less sensitivity to variations in alignment or dimensions of various cell elements (linewidths) thereby providing an improved floating gate memory cell operating window over a wide range of processing variations.
It is yet a further object of the present invention to provide a memory cell having an improved operating window thereby lowering the operating voltage requirements and providing a tighter distribution of the voltages required to operate an array of memory cells.